1. Field of Invention
The present invention relates to a circuit for controlling the slew rate of the output voltage of a driver in a push-pull configuration.
2. Background of the Relevant Art
It is important to be able to control the slew rate of the output signal of a driver so that the edge transitions of the output signal are neither too fast nor too slow, in order to ensure accurate control of the output waveform as the load connected to the driver varies.
In particular, for RS232 serial interfaces, for example, the load is of the ohmic-capacitive type.
When operating at data rates on the order of 100 kbps, it is important to be able to precisely control the slew rate of the output signal of the driver in order to ensure a desired data transmission rate.
A known solution for controlling the slew rate of the output signal of a driver is shown in FIG. 1, wherein the input signal Tin of the driver is input to a first positive boost circuit 1, which boosts the signal Tin to the voltage V+ obtained from a charge pump circuit, and is also input to a second negative boost circuit 2, which pulls the level of the signal Tin down to the level V- by inverting the voltage obtained from the charge pump circuit.
Two capacitors C1 and C2 are respectfully connected between the output signal Tout of the driver and gate terminals of a PMOS transistor P1 and of an NMOS transistor N1. The gate or control electrode of transistors P1 and N1 are respectively connected to the output of positive boost circuit 1 and negative boost circuit 2. Transistors P1 and N1 form the final stage of the known driver circuit.
The load, of the ohmic-capacitive type and designated by the reference numeral 3, is driven by the output signal Tout.
The known driver circuit is not without its shortcomings.
First, in order to be able to use capacitors C1 and C2, whose capacitances are not excessively high, the connection thereof between the output terminal and the gate terminal of their corresponding final stage transistor is able to exploit the Miller effect stemming from the amplification provided by final stage transistors P1 and N1. Because it is impossible to provide precise control of the amplification of final stage transistors P1 and N1, the control over the slew rate of output signal Tout is imprecise.
In operation, when the final stage transistor P1 is on, the transistor N1 is off. Accordingly, the capacitor C2 that intervenes during the rising edge of the output signal Tout is subjected to a potential difference given by EQU V2=(V+)-Vds(P1)-(V-),
where V2 is the voltage across capacitor C2 and Vds(P1) is the voltage between the drain terminal and the source terminal of the transistor P1.
On the contrary, in the second mode wherein the transistor P1 is in the off state and the transistor N1 in the on state, the capacitor C1 is subjected to a potential difference given by EQU V1=(V+)-[(V-)+Vds(N1)],
where V1 is the voltage across capacitor C1 and Vds(N1) is the voltage between the drain terminal and the source terminal of the transistor N1.
In the context of the known driver being part of an RS232 serial interface, the difference in voltage between V+ and V- is high and it is therefore necessary to use high-voltage capacitors for capacitors C1 and C2. Consequently, the area occupied by the capacitors C1 and C2 in an integrated circuit chip substantially increases.
Further, the charging and discharging currents for the two capacitors C1 and C2 cannot be accurately controlled, since they are respectively coupled to the output of the positive and negative boost circuits 1 and 2.